AMD “Zen 6” Processor Families to Use a Mix of TSMC N2 and N3 Nodes

AMD’s upcoming Zen 6 CPU family will leverage a combination of TSMC’s N3 and N2 process nodes, according to slide decks shared with engineers at three leading motherboard vendors. These documents outline five distinct silicon lines set to arrive in late 2026 across servers, desktops, and notebooks. On the server front, the EPYC “Venice” lineup splits into Venice classic for general‑purpose deployments and Venice dense for high‑density cloud racks. Both variants use TSMC’s custom‑tuned N2P process, offering an 8-10% clock‑speed boost over today’s N3E. At the same time, each classic die grows to 12 Zen 6 cores, and each dense die houses 32 Zen 6c cores, enabling up to 256‑core, 512-threaded dense packages when eight dies are interconnected via the existing organic interposer.

For client systems, AMD has adopted codenames that hint at their intended usage profiles. “Olympic Ridge” will drive the Ryzen 10000 desktop series on the N2P node, while “Gator Range” targets gaming laptops exceeding 55 W. The mainstream thin‑and‑light segment will be served by “Medusa Point,” featuring a hybrid design that pairs an N2P compute tile with an N3P I/O tile, with entry‑level models opting for a cost‑efficient monolithic N3P die. A more detailed “Medusa Halo” and the budget‑oriented “Bumblebee” series are also in the roadmap, though their process assignments remain under review. AMD and TSMC’s close co‑optimization of metal layers and libraries means the final silicon closely resembles an “N2‑AMD” stack rather than a standard N2P node. First silicon is expected back from the fab before Christmas, with volume ramps timed for the back‑to‑school 2026 notebook cycle and a subsequent server refresh wave.