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PCI-SIG Releases PCIe 7.0 Specification With Up To 128 GT/s Transfer Rate, Industry’s First PCIe Optical Solution Based on 7.0 Spec

PCI-SIG Releases PCIe 7.0 Specification With Up To 128 GT/s Transfer Rate, Industry’s First PCIe Optical Solution Based on 7.0 Spec

PCI-SIG has officially released the specifications for PCIe 7.0 while offering the industry’s first PCIe Optical Solution that enables higher PCIe speeds.

PCI-SIG Empowers The Next-Generation of AI With Faster 128 GT/s PCIe 7.0 Platform

Press Release: PCI-SIG today announced the official release of the PCI Express (PCIe) 7.0 specification, reaching 128.0 GT/s, to members. The PCIe 7.0 specification targets data-driven applications like AI/ML, 800G Ethernet, cloud, and Quantum computing. Pathfinding for the PCIe 8.0 specification is already in progress to continue supporting the industry’s investments and product roadmaps in the PCIe technology ecosystem.

Image Source: PCI-SIG

PCI Express 7.0 Specification Features

  • Delivers 128.0 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
  • Utilizes PAM4 (Pulse Amplitude Modulation with 4 levels) signaling and Flit-based encoding
  • Provides improved power efficiency
  • Maintains backwards compatibility with previous generations of PCIe technology
Image Source: PCI-SIG

“PCIe technology has served as the high-bandwidth, low-latency IO interconnect of choice for over two decades, and we are pleased to announce the release of the PCIe 7.0 specification, which continues our long-standing tradition of doubling the IO bandwidth every three years,” said Al Yanes, PCI-SIG President and Chairperson. “As artificial intelligence applications continue to scale rapidly, the next generation of PCIe technology meets the bandwidth demands of data-intensive markets deploying AI, including hyperscale data centers, high performance computing (HPC), automotive, and military/aerospace.”

“It’s a special occasion when a PCIe specification hits the final version,” observed Ian Cutress, Chief Analyst and CEO, More Than Moore. The rise in the demand for both compute and networking, enabled through PCIe technology, is at an all-time high, despite the complexities of creating standards in the industry around high-speed signaling. Datacenters are ready to start deploying networks built on PCIe 7.0 technology, and almost every ASIC company I talk to is already engaged with the IP providers and is set to take advantage. Even with the popularity and focus that went into PCIe 6.0 deployment, the PCIe 7.0 specification has more enthusiasm than any previous version.”

via PCI-SIG

Image Source: PCI-SIG

[Editor’s Note] In terms of actual bandwidth, PCIe 7.0 will deliver a bit-rate of up to 128.0 GT/s and a bi-directional bandwidth of up to 512 GB/s through an x16 lane configuration. PCIe 7.0 also uses a PAM4 (Pulse Amplitude Modulation with 4 levels) signaling and Flit-based encoding. The tech will enable higher power efficiency and maintain backward compatibility with previous generations of PCIe technology.

Image Source: PCI-SIG

In addition to the specification announcement, PCI-SIG has also announced a new optical interconnect specification revision to enable higher PCI Express (PCIe) technology performance. The Optical Aware Retimer Engineering Change Notice (ECN) amends the PCIe 6.4 specification and the new PCIe 7.0 specification to include a PCIe retimer-based solution, providing the first industry-standardized way to implement PCIe technology over optical fiber.

Image Source: PCI-SIG

Optical Aware Retimer ECN

  • Seamlessly enables various optical technologies for optical interconnection between existing PCIe 6.4 and 7.0 specification-compliant Switch, Root-Complex, and Endpoint silicon designs
  • Grants extended reach across racks and pods
  • Allows multiplexing and data mapping across electrical and optical domains
  • Enables more compact implementations than electrical copper solutions

The Optical Retimer ECN is now available for PCI-SIG members to download in the PCIe 6.4 and 7.0 specifications here. PCI-SIG invites interested parties to participate in its technical workgroups. The PCIe 7.0 standard will complete its pre-FYI testing by 2027 and the initial integrator list is projected for 2028.

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